This invention relates to noise reduction in integrated circuits and, more particularly, to a method and apparatus for reducing the transient noise generated during operation of the output drivers of an integrated circuit.
Digital data processing systems are typically built from integrated circuits that incorporate on a single chip thousands of binary circuit elements such as registers, logic gates and input receiver and output driver circuits. Generally, an integrated circuit chip processes a number of parallel channels of data, e.g. eight, sixteen or thirty-two. The integrated circuits are mounted on printed circuit boards having conductive paths that interconnect the input and output circuits on the integrated circuit chips and supply thereto operating power supply potentials. An integrated circuit chip is conventionally incorporated into a package that has a number of leads connecting the integrated circuits on the chip to the printed circuit board. Since the output driver channels of an integrated circuit chip are connected through the package leads "off chip" to the conductive paths on the printed circuit board, they must be designed to drive a large capacitive load, e.g., 50 to 100 pf.
An integrated circuit chip has parasitic inductance representative of the inductance of the conductive paths from the integrated circuit chip to the output pins of its package. It is common practice in the design of integrated circuit chips to employ a single package pin for the connections of all or many of the parallel channels to the power supply potentials off chip. In such case, the output drivers of all the channels driven toward a power supply potential during any single switching interval contribute to the transient noise due to package inductance.
During the past several years, there has been increasing awareness of the problems resulting from the transient noise generated within large scale integrated (LSI) circuits. The major problems occur from the simultaneous switching of multiply output drivers designed to drive high capacitance loads, such as the data bus of microprocessors or the address bus of a large memory array. Under most conditions, the transient current at power supply nodes resulting from switching multiple output drivers, tends to be additive. Therefore, even a small value of parasitic inductance produces series noise problems.
The problem has become more acute and apparent, because evolving technology tends to produce LSI circuits with higher performance. By decreasing the delay of the output driver, by increasing the effective data rate on the outputs, or by increasing the specified load capacitance, then, more electric charge must be transferred in a shorter interval of time.
In application Ser. No. 07/161,469, now U.S. Pat. No. 4,947,063 filed Feb. 26, 1988, by Timothy G. O'Shannesy et al. and assigned to the assignee of the present application, transient noise is reduced by employing a predriver stage that applies an approximately linear ramp shaped control voltage to the gate of a MOS transistor output driver stage during the entire transition interval between binary states. This tends to minimize the rate of change of the load current during the transition interval and therefore the transient noise created by the parasitic inductance.